1. Field of the Invention
This invention relates to packaging substrates and methods of fabricating the same, and, more particularly, to a coreless packaging substrate and a method of fabricating the same.
2. Description of Related Art
With the rapid development of electronic industry, electronic products gradually move toward a trend of multi-functional and high performance. Currently, structure of semiconductor package has been developed into various types. For example, wire-bonding type or flip-chip type, is to set semiconductor chip on a packaging substrate. Besides, the semiconductor chip is connected to packaging substrate by bonding wires or solder bumps.
In order to meet the demand of high integration and miniaturization for connection and carrying of more active, passive components and wires, packaging substrate gradually evolves from double-layer board to multi-layer board. So that circuit area of packaging substrate can be broaden within limited space by interlayer connection, and can satisfy the operation requirement of integrated circuit with high circuit density. Moreover, thickness of packaging substrate can be lowered and the purpose of low-profiled and compact-sized structure and improved electric function can be achieved.
In prior art, packaging substrate is composed of core board with internal circuit and symmetric, built-up circuit structure. Owing to the thickness increment of overall structure using core board, it is difficult to satisfy the needs of improving function while shrinking substrate volume.
Thus, a coreless packaging substrate has been developed. Catch the trend of high-frequency and miniaturization by shortening circuit length and thickness of overall structure. As shown in FIG. 1, a coreless packaging substrate 1 is fabricated by the following steps of: forming a first dielectric layer 120a on a carrier board (not shown) and forming a first circuit layer 11 on the first dielectric layer 120a; forming a built-up structure 12 on the first dielectric layer 120a and the first circuit layer 11, the built-up structure 12 having second, third and fourth dielectric layers 120b, 120c and 120d, on which second circuit layers 121 that are electrically connected to one another by conductive vias 122 are formed; removing the carrier board to expose the first dielectric layer 120a; forming a solder mask 14a on the first dielectric layer 120a, and forming another solder mask 14b on the fourth dielectric layer 120d and the second circuit layer 121; forming openings 140a on the solder mask 14a and the first dielectric layer 120a to expose a portion of the first circuit layer 11, and forming another openings 140b on the solder mask 14b to expose a portion of the second circuit layer 121; and forming metal bumps 13a and 13b in the openings 140a and 140b, respectively, for bottom solder balls 15a and top solder balls 15b to be combined with, respectively, wherein a chip (not shown) may be disposed on the top solder balls 15b, and a circuit board (not shown) may be disposed on the bottom solder balls 15a. In the prior art, the packaging substrate 1 is fabricated in a bottom-up manner. In other words, the bottom side (i.e., a surface that is in contact with the carrier board) of packaging substrate 1 is fabricated first, then the intermediate components, such as the first to fourth dielectric layers 120a to 120d, are fabricated sequentially, and the metal bump 13b and the solder mask 14b are fabricated in the final step. In short, the packaging substrate 1 is fabricated from one side where the bottom solder balls 15a are implanted to the other side where the chip may be disposed.
Wherein, one curing process needs to be performed whenever one of the dielectric layers 120a to 120d is formed, in order to cure the newly formed and half cured dielectric layers 120a to 120d. Besides, the greater the number of the curing process performed is, the more complete the gathering and shrinking of molecules in one of the dielectric layers 120a to 120d become. The curing processes affect all the dielectric layers. In the packaging substrate 1, the curing process is performed four, three, two and one time on the first to fourth dielectric layers 120a to 120d, respectively.
As above-mentioned, because of the different number of the curing process performed on the first to fourth dielectric layers 120a to 120d, the first to fourth dielectric layers 120a to 120d have different residual stress to gather and shrink. Since the curing process is performed on the first dielectric layer 120a four times and is performed on the fourth dielectric layer 120d one time only, the first dielectric layer 120a has less residual stress than the fourth dielectric layer 120d. Because each dielectric layer exerts centralizing, residual stress on the packaging substrate 1, in the prior art the packaging substrate 1 presents a phenomenon of warpage that the fourth dielectric layer side 120d is sunken and the first dielectric layer side 120a is bulged. To be more detailed, the packaging substrate 1 in which the chip-disposing side is an upper side is in the shape of “smile,” which is a characteristic of this kind of process, and the warpage phenomenon causes trouble to packaging substrate manufacture and to following packaging process, and then affects yield.
Notice that solder masks 14a and 14b are disposed on the first dielectric layer 120a and fourth dielectric layer 120d, respectively, and because the opening 140a of the solder masks on the lower side 14a is greater than the opening 140b of the solder mask on the upper side 14b, the actual covered area by the solder mask on the lower side 14a is smaller than that by the solder mask on the upper side 14b. That is, the upper solder mask 14b has more material than the lower solder mask 14a. The solder masks 14a and 14b also have residual stress to gather and shrink, so that the pull force from the upper solder mask 14b exerted on the packaging substrate is greater than that from the lower solder mask 14a, which causes warpage of packaging substrate 1 more serious (as indicated by a dotted line in FIG. 1).
In addition, the solder mask in the prior art and the external circuit layer it covers are non-coplanar, which also affects the yield and density of the package.
Therefore, how to overcome the over-warpage problem of the prior art is becoming the topic in urgent need to be solved.